mirror of
https://github.com/Xevion/easy7zip.git
synced 2025-12-07 16:07:05 -06:00
23.01
This commit is contained in:
Igor Pavlov
Kornel
243
C/CpuArch.h
243
C/CpuArch.h
@@ -1,8 +1,8 @@
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/* CpuArch.h -- CPU specific code
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2021-07-13 : Igor Pavlov : Public domain */
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2023-04-02 : Igor Pavlov : Public domain */
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#ifndef __CPU_ARCH_H
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#define __CPU_ARCH_H
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#ifndef ZIP7_INC_CPU_ARCH_H
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#define ZIP7_INC_CPU_ARCH_H
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#include "7zTypes.h"
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@@ -51,7 +51,13 @@ MY_CPU_64BIT means that processor can work with 64-bit registers.
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|| defined(__AARCH64EB__) \
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|| defined(__aarch64__)
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#define MY_CPU_ARM64
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#define MY_CPU_NAME "arm64"
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#ifdef __ILP32__
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#define MY_CPU_NAME "arm64-32"
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#define MY_CPU_SIZEOF_POINTER 4
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#else
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#define MY_CPU_NAME "arm64"
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#define MY_CPU_SIZEOF_POINTER 8
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#endif
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#define MY_CPU_64BIT
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#endif
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@@ -68,8 +74,10 @@ MY_CPU_64BIT means that processor can work with 64-bit registers.
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#define MY_CPU_ARM
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#if defined(__thumb__) || defined(__THUMBEL__) || defined(_M_ARMT)
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#define MY_CPU_ARMT
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#define MY_CPU_NAME "armt"
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#else
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#define MY_CPU_ARM32
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#define MY_CPU_NAME "arm"
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#endif
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/* #define MY_CPU_32BIT */
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@@ -103,6 +111,8 @@ MY_CPU_64BIT means that processor can work with 64-bit registers.
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|| defined(__PPC__) \
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|| defined(_POWER)
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#define MY_CPU_PPC_OR_PPC64
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#if defined(__ppc64__) \
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|| defined(__powerpc64__) \
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|| defined(_LP64) \
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@@ -123,12 +133,15 @@ MY_CPU_64BIT means that processor can work with 64-bit registers.
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#endif
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#if defined(__sparc64__)
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#define MY_CPU_NAME "sparc64"
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#define MY_CPU_64BIT
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#elif defined(__sparc__)
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#define MY_CPU_NAME "sparc"
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/* #define MY_CPU_32BIT */
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#if defined(__riscv) \
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|| defined(__riscv__)
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#if __riscv_xlen == 32
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#define MY_CPU_NAME "riscv32"
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#elif __riscv_xlen == 64
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#define MY_CPU_NAME "riscv64"
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#else
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#define MY_CPU_NAME "riscv"
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#endif
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#endif
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@@ -194,6 +207,9 @@ MY_CPU_64BIT means that processor can work with 64-bit registers.
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#error Stop_Compiling_Bad_Endian
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#endif
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#if !defined(MY_CPU_LE) && !defined(MY_CPU_BE)
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#error Stop_Compiling_CPU_ENDIAN_must_be_detected_at_compile_time
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#endif
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#if defined(MY_CPU_32BIT) && defined(MY_CPU_64BIT)
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#error Stop_Compiling_Bad_32_64_BIT
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@@ -250,6 +266,67 @@ MY_CPU_64BIT means that processor can work with 64-bit registers.
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#ifdef __has_builtin
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#define Z7_has_builtin(x) __has_builtin(x)
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#else
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#define Z7_has_builtin(x) 0
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#endif
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#define Z7_BSWAP32_CONST(v) \
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( (((UInt32)(v) << 24) ) \
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| (((UInt32)(v) << 8) & (UInt32)0xff0000) \
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| (((UInt32)(v) >> 8) & (UInt32)0xff00 ) \
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| (((UInt32)(v) >> 24) ))
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#if defined(_MSC_VER) && (_MSC_VER >= 1300)
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#include <stdlib.h>
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/* Note: these macros will use bswap instruction (486), that is unsupported in 386 cpu */
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#pragma intrinsic(_byteswap_ushort)
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#pragma intrinsic(_byteswap_ulong)
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#pragma intrinsic(_byteswap_uint64)
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#define Z7_BSWAP16(v) _byteswap_ushort(v)
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#define Z7_BSWAP32(v) _byteswap_ulong (v)
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#define Z7_BSWAP64(v) _byteswap_uint64(v)
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#define Z7_CPU_FAST_BSWAP_SUPPORTED
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#elif (defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3))) \
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|| (defined(__clang__) && Z7_has_builtin(__builtin_bswap16))
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#define Z7_BSWAP16(v) __builtin_bswap16(v)
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#define Z7_BSWAP32(v) __builtin_bswap32(v)
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#define Z7_BSWAP64(v) __builtin_bswap64(v)
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#define Z7_CPU_FAST_BSWAP_SUPPORTED
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#else
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#define Z7_BSWAP16(v) ((UInt16) \
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( ((UInt32)(v) << 8) \
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| ((UInt32)(v) >> 8) \
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))
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#define Z7_BSWAP32(v) Z7_BSWAP32_CONST(v)
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#define Z7_BSWAP64(v) \
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( ( ( (UInt64)(v) ) << 8 * 7 ) \
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| ( ( (UInt64)(v) & ((UInt32)0xff << 8 * 1) ) << 8 * 5 ) \
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| ( ( (UInt64)(v) & ((UInt32)0xff << 8 * 2) ) << 8 * 3 ) \
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| ( ( (UInt64)(v) & ((UInt32)0xff << 8 * 3) ) << 8 * 1 ) \
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| ( ( (UInt64)(v) >> 8 * 1 ) & ((UInt32)0xff << 8 * 3) ) \
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| ( ( (UInt64)(v) >> 8 * 3 ) & ((UInt32)0xff << 8 * 2) ) \
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| ( ( (UInt64)(v) >> 8 * 5 ) & ((UInt32)0xff << 8 * 1) ) \
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| ( ( (UInt64)(v) >> 8 * 7 ) ) \
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)
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#endif
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#ifdef MY_CPU_LE
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#if defined(MY_CPU_X86_OR_AMD64) \
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|| defined(MY_CPU_ARM64)
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@@ -269,13 +346,11 @@ MY_CPU_64BIT means that processor can work with 64-bit registers.
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#define GetUi32(p) (*(const UInt32 *)(const void *)(p))
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#ifdef MY_CPU_LE_UNALIGN_64
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#define GetUi64(p) (*(const UInt64 *)(const void *)(p))
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#define SetUi64(p, v) { *(UInt64 *)(void *)(p) = (v); }
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#endif
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#define SetUi16(p, v) { *(UInt16 *)(void *)(p) = (v); }
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#define SetUi32(p, v) { *(UInt32 *)(void *)(p) = (v); }
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#ifdef MY_CPU_LE_UNALIGN_64
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#define SetUi64(p, v) { *(UInt64 *)(void *)(p) = (v); }
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#endif
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#else
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@@ -302,51 +377,26 @@ MY_CPU_64BIT means that processor can work with 64-bit registers.
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#endif
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#ifndef MY_CPU_LE_UNALIGN_64
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#ifndef GetUi64
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#define GetUi64(p) (GetUi32(p) | ((UInt64)GetUi32(((const Byte *)(p)) + 4) << 32))
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#endif
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#ifndef SetUi64
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#define SetUi64(p, v) { Byte *_ppp2_ = (Byte *)(p); UInt64 _vvv2_ = (v); \
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SetUi32(_ppp2_ , (UInt32)_vvv2_); \
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SetUi32(_ppp2_ + 4, (UInt32)(_vvv2_ >> 32)); }
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SetUi32(_ppp2_ , (UInt32)_vvv2_) \
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SetUi32(_ppp2_ + 4, (UInt32)(_vvv2_ >> 32)) }
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#endif
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#if defined(MY_CPU_LE_UNALIGN) && defined(Z7_CPU_FAST_BSWAP_SUPPORTED)
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#define GetBe32(p) Z7_BSWAP32 (*(const UInt32 *)(const void *)(p))
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#define SetBe32(p, v) { (*(UInt32 *)(void *)(p)) = Z7_BSWAP32(v); }
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#ifdef __has_builtin
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#define MY__has_builtin(x) __has_builtin(x)
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#else
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#define MY__has_builtin(x) 0
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#if defined(MY_CPU_LE_UNALIGN_64)
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#define GetBe64(p) Z7_BSWAP64 (*(const UInt64 *)(const void *)(p))
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#endif
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#if defined(MY_CPU_LE_UNALIGN) && /* defined(_WIN64) && */ defined(_MSC_VER) && (_MSC_VER >= 1300)
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/* Note: we use bswap instruction, that is unsupported in 386 cpu */
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#include <stdlib.h>
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#pragma intrinsic(_byteswap_ushort)
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#pragma intrinsic(_byteswap_ulong)
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#pragma intrinsic(_byteswap_uint64)
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/* #define GetBe16(p) _byteswap_ushort(*(const UInt16 *)(const Byte *)(p)) */
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#define GetBe32(p) _byteswap_ulong (*(const UInt32 *)(const void *)(p))
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#define GetBe64(p) _byteswap_uint64(*(const UInt64 *)(const void *)(p))
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#define SetBe32(p, v) (*(UInt32 *)(void *)(p)) = _byteswap_ulong(v)
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#elif defined(MY_CPU_LE_UNALIGN) && ( \
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(defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3))) \
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|| (defined(__clang__) && MY__has_builtin(__builtin_bswap16)) )
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/* #define GetBe16(p) __builtin_bswap16(*(const UInt16 *)(const void *)(p)) */
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#define GetBe32(p) __builtin_bswap32(*(const UInt32 *)(const void *)(p))
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#define GetBe64(p) __builtin_bswap64(*(const UInt64 *)(const void *)(p))
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#define SetBe32(p, v) (*(UInt32 *)(void *)(p)) = __builtin_bswap32(v)
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#else
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#define GetBe32(p) ( \
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@@ -355,8 +405,6 @@ MY_CPU_64BIT means that processor can work with 64-bit registers.
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((UInt32)((const Byte *)(p))[2] << 8) | \
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((const Byte *)(p))[3] )
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#define GetBe64(p) (((UInt64)GetBe32(p) << 32) | GetBe32(((const Byte *)(p)) + 4))
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#define SetBe32(p, v) { Byte *_ppp_ = (Byte *)(p); UInt32 _vvv_ = (v); \
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_ppp_[0] = (Byte)(_vvv_ >> 24); \
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_ppp_[1] = (Byte)(_vvv_ >> 16); \
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@@ -365,50 +413,83 @@ MY_CPU_64BIT means that processor can work with 64-bit registers.
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#endif
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#ifndef GetBe64
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#define GetBe64(p) (((UInt64)GetBe32(p) << 32) | GetBe32(((const Byte *)(p)) + 4))
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#endif
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#ifndef GetBe16
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#define GetBe16(p) ( (UInt16) ( \
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((UInt16)((const Byte *)(p))[0] << 8) | \
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((const Byte *)(p))[1] ))
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#endif
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#if defined(MY_CPU_BE)
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#define Z7_CONV_BE_TO_NATIVE_CONST32(v) (v)
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#define Z7_CONV_LE_TO_NATIVE_CONST32(v) Z7_BSWAP32_CONST(v)
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#define Z7_CONV_NATIVE_TO_BE_32(v) (v)
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#elif defined(MY_CPU_LE)
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#define Z7_CONV_BE_TO_NATIVE_CONST32(v) Z7_BSWAP32_CONST(v)
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#define Z7_CONV_LE_TO_NATIVE_CONST32(v) (v)
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#define Z7_CONV_NATIVE_TO_BE_32(v) Z7_BSWAP32(v)
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#else
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#error Stop_Compiling_Unknown_Endian_CONV
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#endif
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#if defined(MY_CPU_BE)
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#define GetBe32a(p) (*(const UInt32 *)(const void *)(p))
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#define GetBe16a(p) (*(const UInt16 *)(const void *)(p))
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#define SetBe32a(p, v) { *(UInt32 *)(void *)(p) = (v); }
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#define SetBe16a(p, v) { *(UInt16 *)(void *)(p) = (v); }
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#define GetUi32a(p) GetUi32(p)
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#define GetUi16a(p) GetUi16(p)
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#define SetUi32a(p, v) SetUi32(p, v)
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#define SetUi16a(p, v) SetUi16(p, v)
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#elif defined(MY_CPU_LE)
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#define GetUi32a(p) (*(const UInt32 *)(const void *)(p))
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#define GetUi16a(p) (*(const UInt16 *)(const void *)(p))
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#define SetUi32a(p, v) { *(UInt32 *)(void *)(p) = (v); }
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#define SetUi16a(p, v) { *(UInt16 *)(void *)(p) = (v); }
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#define GetBe32a(p) GetBe32(p)
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#define GetBe16a(p) GetBe16(p)
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#define SetBe32a(p, v) SetBe32(p, v)
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#define SetBe16a(p, v) SetBe16(p, v)
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#else
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#error Stop_Compiling_Unknown_Endian_CPU_a
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#endif
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#if defined(MY_CPU_X86_OR_AMD64) \
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|| defined(MY_CPU_ARM_OR_ARM64) \
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|| defined(MY_CPU_PPC_OR_PPC64)
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#define Z7_CPU_FAST_ROTATE_SUPPORTED
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#endif
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#ifdef MY_CPU_X86_OR_AMD64
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typedef struct
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{
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UInt32 maxFunc;
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UInt32 vendor[3];
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UInt32 ver;
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UInt32 b;
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UInt32 c;
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UInt32 d;
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} Cx86cpuid;
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enum
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{
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CPU_FIRM_INTEL,
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CPU_FIRM_AMD,
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CPU_FIRM_VIA
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};
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void MyCPUID(UInt32 function, UInt32 *a, UInt32 *b, UInt32 *c, UInt32 *d);
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BoolInt x86cpuid_CheckAndRead(Cx86cpuid *p);
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int x86cpuid_GetFirm(const Cx86cpuid *p);
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#define x86cpuid_GetFamily(ver) (((ver >> 16) & 0xFF0) | ((ver >> 8) & 0xF))
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#define x86cpuid_GetModel(ver) (((ver >> 12) & 0xF0) | ((ver >> 4) & 0xF))
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#define x86cpuid_GetStepping(ver) (ver & 0xF)
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BoolInt CPU_Is_InOrder(void);
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void Z7_FASTCALL z7_x86_cpuid(UInt32 a[4], UInt32 function);
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UInt32 Z7_FASTCALL z7_x86_cpuid_GetMaxFunc(void);
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#if defined(MY_CPU_AMD64)
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#define Z7_IF_X86_CPUID_SUPPORTED
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#else
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#define Z7_IF_X86_CPUID_SUPPORTED if (z7_x86_cpuid_GetMaxFunc())
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#endif
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BoolInt CPU_IsSupported_AES(void);
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BoolInt CPU_IsSupported_AVX(void);
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BoolInt CPU_IsSupported_AVX2(void);
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BoolInt CPU_IsSupported_VAES_AVX2(void);
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BoolInt CPU_IsSupported_CMOV(void);
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BoolInt CPU_IsSupported_SSE(void);
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BoolInt CPU_IsSupported_SSE2(void);
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BoolInt CPU_IsSupported_SSSE3(void);
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BoolInt CPU_IsSupported_SSE41(void);
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BoolInt CPU_IsSupported_SHA(void);
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@@ -433,8 +514,8 @@ BoolInt CPU_IsSupported_AES(void);
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#endif
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#if defined(__APPLE__)
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int My_sysctlbyname_Get(const char *name, void *buf, size_t *bufSize);
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int My_sysctlbyname_Get_UInt32(const char *name, UInt32 *val);
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int z7_sysctlbyname_Get(const char *name, void *buf, size_t *bufSize);
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int z7_sysctlbyname_Get_UInt32(const char *name, UInt32 *val);
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#endif
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EXTERN_C_END
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